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- Cost efficient JTAG-ToolFor interactive board level debugging and production tests
- IO-FilteringObserve IOs of interest only
- Pin-File parsingUse your HDL top-level pin names to find signals quickly
- Free with every Hpe®_midi systemEvery Hpe®_midi system comes with powerful and free software tools, including Hpe®_JTAG
- Scripting interface
For production tests and all repetitive tasks
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Have you ever attempted to measure signals between two ball grid arrays and then noticed that you forgot to insert test pads?
Has the price of JTAG tools kept y
ou from using Boundary Scan Tests?
With Hpe®_JTAG Gleichmann Electronics Research
introduces a cost efficient JTAG tool allowing you to debug and test your PCBs and ICs. Hpe®_JTAG gives the design engineer
full control over the logical states of any I/O-pin or register that
is accessible via Boundary Scan at a fraction of the cost of high-end
JTAG tools.
Opposed to most low-cost JTAG tools, Hpe®_JTAG is fully scriptable, hence tests can be automated for production.
The x-ray pictures below show two of the most common problems designers might run into when using BGAs: shorts and open solder joints. |
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Not every designer has access to an x-ray machine and if these signals are not routed to the top or bottom layer of the PCB, JTAG might be the only
way to find these sorts of problems.
Hpe®_JTAG enables designers to debug their PCBs interactively (without the need to program a design into the PLDs),
observe and debug their PLD designs, write scripts for all repetitive tasks
and even setup production tests at a fraction of the cost of high-end JTAG tools. |
Hpe®_JTAG supports the following JTAG instructions:
- SAMPLE: The SAMPLE instruction is used to get a snapshot of the current pin states of a device in the JTAG chain.
It does not influence the device operation.
- EXTEST: The EXTEST instruction is used to check a connection between devices in one JTAG chain.
The values of
output pins can be set and the values of input pins can be read.
- INTEST: The INTEST instruction is used to check the internal functionality of a device in the JTAG chain.
The values of input pins
can be set and the values of output pins can be read. Note that the availability of the
INTEST instruction depends on the devices' capabilities.
Hpe®_JTAG provides a graphic user interface, but also powerful Python-scripting capabilities. The screenshot below shows an example
for a
scan chain containing two JTAG compatible devices that are represented by the two tabs. Instead of graphically representing huge ball
grid arrays
with more than thousand IOs each, a filter function allows the user to display only IOs that are currently of interest. |
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IO-Filtering:
Observe IOs of interest only
Pin-File parsing:
Use your HDL top-level pin names to find signals quickly
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