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The Turbo for FPGA-Design |
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SEmulation: The Advantage
Higher design security
Shorter development times
Fast switch between simulation and emulation
Same configuration for simulation and emulation
No simulation models for hardware (Hardware in the Loop)
No additional hardware cost
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Download Whitepaper |
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Introduction
With the SEmulator®, GE-Research introduces a new method of FPGA / ASIC design, which promise
shorter development times and higher design
security for lower costs.
With complex processor systems, complete interface structures and design, by dimensions up to 3
million ASIC-gates per chip,
FPGA’s dominate the semiconductor market with their flexibility and
reconfigurable architecture.
Time pressures on the engineer with shorter design-cycles allow for no failures.
Function and time response of the finished semiconductors have to
be right first time after
synthesizing in silicon as revisions costs money.
Nowadays FPGA’s will be developed in two steps: First step: HDL-functional blocks are simulated,
individually at first, then as a whole. Second step:
The FPGA will be synthesized and tested in a rapid
prototyping system. SEmulation combines the two
steps and allows the step-by-step transfer of the
functional blocks from the simulator (software) into
the FPGA (hardware), so without leaving the
development environment the simulations and thus
the
development time will be shortened. Currently
the Simulation and Emulation environments are
separate and not always compatible resulting in
engineering time
being wasted getting simulated
code to run in the emulator environment. Using the
SEmulator®, mistakes and insecurities are excluded
as we simulate on the
target hardware. Our
SEmulator® also allows the engineer to introduce into
the simulation any external component, (this is
“hardware in the loop”). For the
developer this
means functional “First Silicon” and therefore a
reduction of development costs, as well as an
increased reactivity on market requirements
SEmulator® – Bridging the gap between Simulation and Emulation
SEmulator® is a made-up word that combines the words Simulator and Emulator. It describes the basic functionality of the SEmulator® very well. The SEmulator®
provides bridging functionality between the
domain of digital hardware simulation and the world of FPGA prototyping. Design blocks can easily be
moved between
this two domains.
Nowadays digital hardware is described using hardware description languages like VHDL or Verilog.
These descriptions are simulated together with a problem
specific test bench (also written in a
hardware description language). The initial functional verification of this design is done via simulation.
This approach is a
must for the complex designs that are developed today.
The real aim for the hardware designer is not the simulation. It’s running the design on real hardware.
The step from simulation to the real hardware prototype is
a huge one and should not be
underestimated.
When the simulation results are satisfactory, the designer takes the whole design and downloads the
synthesized netlist into his FPGA prototyping board. Then
he needs a logic analyzer and plenty of time
to locate and fix any bugs in his design.
The SEmulator® approach enables the designer to use the prototyping FPGA board at an
early state of the design flow.
The SEmulator® allows design blocks to be moved into the FPGA and
to cosimulate them with the actual developed design blocks in the HDL simulator. |
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